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| MIL-W-85057 (AS )
3.4.1.1.5 capacity and Expansion Provisions. The memory storage capacity
provided shall be 16,384 words. The capability to expand the memory storage
capacity to 32,768 words shall be provided wlthin the existing structure,
within the existing power supply, logic and timing capability, and environmental
requirements. The computer memory shall be fully tested for 32,768 word operation.
3.4.1.2 Instruction Repertoire. The WDC shall be capable of executing
an instruction repertoire consisting of 43 instructions as identified in
Table II of the following types:
(1) Loading/Storing of Registers.
(2) Arithmetic Operations.
(3) Logical Operations.
(4) Shift Operations.
(5) Branch (jump) Operations.
(6) I/0 Operations.
Table III contains the complete DC Instruction set, lncluding all addressing codes.
3.4.1.3 Timing. The timing shown shall be for Instruction, fetch,
operand fetch (if required), and Instruction execution. For Indirect
Addressing, 1.0s shall be added to the time given. For Indirect and
Tally, 1.5s shall be added. For Immediate Addressing, 0.5 s shall
be subtracted. For base register, 0.25s shall be added. For Modify
Base (if Base ), 0.25 us shall be added. For Shift Instructions, N/8
us shall be added for N bits of Right Shift when N is even and (N + 1)/8
us when N is odd. For Left Shift, N/4 s shall be added. For Long Format
(RS) Instructions, 1.0 s shall be added. For Branch Indirect (relative
to Sector 2), 0.5 s shall be added. For Branch Indirect (relative to
Base or XC), 0.75 s shall be added. .
As. a minimum, the execution of these instruction types shall provide the
performance specified in Table 21.
3.4.1.4 Input/Output. The WDC shall provide the 1/0 capability that
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is required to implement the electrical interface definition specified in
3.3.13. A summary of the type and quantity of I/0 that shall be provided
is presented in Table IV. As a minimum, the I0 processing of these I/0
types shall provide the performance specified herein.
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