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MIL-W-85057(AS)
3.5.1.7.2 Program Fault Interrupt.  The appearance of a memory parity
error shall generate an interrupt of priority level "I", namely a "break-in"
to memory location 7, as will an attempt to address a non-existent memory
location.  A priority level "1" Interrupt shall initiate a timed logic
path to set the FAULT INDICATOR.
3.5.1.7.3 BITE Failure Interrupt.  When a BITE failure instruction is
executed, a priority level "1" interrupt shall be generated as specified
herein. Execution of a Reset Interface (RI) instruction within 2 milli-
seconds (me) after "break-in" to location 7 shall inhibit setting the FAULT
INDICATOR.
3.5.1.7.4 External Interrupts.
Interrupt levels "2" and "3" shall be
generated by the CIU.
3.5.1.8 System Timing.  The DC shall provide timing signals required to
establish the 50-kilohertz (kHz) timing for CIU I/0 functions.  These shall
be derived from a precision crystal oscillator located within the DC. The
oscillator shell be accurate to within + 100 parts per million (ppm) over
the service conditions of 3.3.9.
3.5.2 Converter-Interface Unit.
The CIU shall perform as specified
herein.
3.5.2.1 General.
The CIU shall provide the following:
(1) Synchro-to-digital signal Converslon.
(2) Analog-to-digital (A/D) signal conversion.
(3) Digital-to-analog (D/A) signal conversion.
(4) Interrupts.
(5) channel status.
(6) 50-kHz serial I/0 channel.
(7) 5 Vdc power for ARBS Control-Indicator.
3.5.2.1.1 Synchro-to-Digital Signal Converter. The CIU shall accept
three separate synchro signal inputs and convert each of these to digital
signals proportional to sin cos under program control.  Synchro
conversion accuracy shall be such that all errors in deriving shell not
exceed + 3 milliradians. This accuracy shall apply over the required
operating temperature range, with maximum signal Input voltages of 11.8 v
mot--mean-square (me) + 10 percent and with an input frequency of 400 Hz
+ 5 percent.
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