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|  MIL-W-85057(AS)
3.5.1.5.3 Quotient Register Q-REG) . The Q-REG shall be a register
that can be loaded from, or into memory, and:
(1) Contains half the source and result of double precision
add and subract.
(2) supplies one parameter for multiply or half the
dividend for divide.
(3) Shall contain half the product.
(4) Contains low half of double word dividend and is linked
with A-REG.
3.5.1.5.4 Instruction Counter Register (IC-REG). The IC-REG shall contain
the absolute address of the next memory location to be fetched as an instruction
at the time that the current instruction is beginning execution. The contents
of this register may be changed with the branch class of instructions.
3.5.1.6 Modes of Addressing. There shall be four modes of addressing
a memory reference: direct, indirect, Indexed, and relative.
3.5.1.6.1 Direct. A part of the instruction word or a second word
following the instruction refers to an absolute memory location. The
minimum amount of memory addressable in this manner shall be 512 words.
3.5.1.6.2 Indirect. A part of the instruction word (DISP) shall be
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added to 512 to the address of a main store location (DISP + 512).
The main store location contains the absolute address of the actual operand.
3.5.1.6.3 Indexed. A part of the instruction word shall be added to
the contents of the to generate the operand l ddress.
3.5.1.6.4 Relative. A part of the instruction word shall be l dded to
the contents of the IC-REG to generate the operand l ddress.
3.5.1.7 Interrupts. The DC shall accept a minimum of 11 interrupts
having at least four priority levels as described below. The CP may inhibit
all interrupts except Power Fail/Restart, Program Fault, and BITE Fail.
3.5.1.7.1 Power Fail/Restart Interrupt. When source power falls outside
acceptable limits specified in the power supply for a period greater than
75s, an interrupt of the priority level "O" shall be initiated. When
power Is reapplied, the computer shall begin operation at the memory
location for a priority level "O" interrupt. This interrupt shall force
a hardware implemented system reset. It shall be possible to force a
level "O" interrupt without cycling power by means of the AGE connector.
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