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| MIL-D-81347C(AS)
Controller shall be in synchronism with the byte clock generated by the MDM. The total number of
byte clocks sent to the Drum Controller will be a multiple of four for each data sector read.
(4) When the last word of a sector has been received by the
Drum Controller, a sector end pulse will be sent to the MDM. This pulse means that the MDM shall
cease reading data and shall send no more byte clocks for that sector. If the MDM is to read the data
sector immediately following the one just finished a sector begin pulse shall be sent simultaneously
with the sector end pulse.
(5) As the data is being read, the MDM shall perform a serial
parity check as was done when the data was written. Each word of data consists of four bytes designa-
ted 1, 2, 3, and 4. The combination of bytes 1 and 2 shall be checked for odd parity and a parity error
shall be indicated by a pulse on the Byte 1/2 Parity Error line. The combination of bytes 3 and 4 shall
be checked for odd parity and a parity error shall be indicated by a pulse on the Byte 3/4 Parity Error
line.
(6) When a track switch is necessary, the track address state
is changed at least eight word clock pulses prior to the time that a sector begin pulse is sent to the
MDM. At no time will a track switch occur within a sector.
Termination of Operation - Normally, read or write operations
3.5.4.4.4.3.3.4.9.3
are terminated by the transmission of a sector end pulse from the Drum Controller and MDM test mode
tests are considered to be completed upon receipt of an MDM test complete pulse from the MDM.
However, termination of an operation shall also occur if the corresponding write, read or MDM test
mode 1, 2 or 3 signals become a Logic O. When this occurs, the MDM shall revert to a standby condition.
When modes are switched (write to read write to MDM test mode, MDM test mode to read etc. ),
there is a period of at least one word time during which mode signals are simultaneously at Logic O.
Data Retention - After data has been written on any specified
3.5.4.4.4.3.3.4.9.4
drum track or tracks and the corresponding track or tracks placed in either a protected or unprotected
state, no data deterioration effects shall occur upon reading the data back when requested at any time
with errors in excess of the specified error rate.
Error Rate - The MDM shall have an average of no more than
3.5.4.4.4.3.3.4.9.5
10
one bit error in 2 X 10 bits recorded and reproduced. The verification of the error rate shall
be based upon using a read to write ratio of four.
Test Operations - The MDM shall have the test capability and
3.5.4.4.4.3.3.4.10
performance as defined in the following paragraphs.
MDM Test Mode 1 Sequence - The MDM Test Mode 1 timing
3.5.4.4.4.3.3.4.10.1
sequence is shown in the MDM Test Mode 1 timing diagram, Figure 158, and is described as follows
for the MDM Track Test Inhibit line at Logic 1. When the MDM Track Test Inhibit line is open circuit,
the sequence is the same except that write and read operations shall begin at word location 1 of each
data track.
(1) The Test Mode 1 signal becomes a Logic 1 and shall re-
main in the Logic 1 state for the entire duration of Test Mode 1 tests.
(2) After the Test Mode 1 signal, the sector begin pulse is
sent to the MDM.
(3) Starting with word location 1091 to and including word
location 1239, the MDM shall write a preamble word and a predetermined word pattern starting with
the first data track and continuing on to the last data track. At this time the MDM shall automatically
switch to a read operation and proceed to read the preamble and word pattern previously written in
word locations 1091 to 1239 at normal threshold sequentially from all data tracks starting with the
first track. With the completion of the first read operation, the MDM shall automatically switch to a
low threshold setting and re- read the test data. Upon completion of the second read operation the MDM
shall automatically switch to a high threshold setting and re-read the test data. At this time the MDM
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