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|  MIL-D-81347C(AS)
shall switch to a write operation and repeat the above procedure for a different predetermined word
pattern. This process shall automatically continue provided no test errors have occurred and until
eight unique word patterns have been written and the high threshold read operation of the last data
pattern on the next to the last data track (track 383) has been completed. The MDM at this time shall
terminate MDM Test Mode 1.
(4) At the completion of Test Mode 1, the MDM shall send to
the Drum Controller a test complete pulse (Logic 1) via the MDM Test Complete line.
(5) If a test error is detected during any of the read opera-
tions, the MDM shall provide an error pulse (Logic 1) to the controller via the MDM Test Error line.
The error pulse shall occur no more than 100 nanoseconds from the leading edge of word clock
No. 1241.
(6) After a delay from the leading edge of the test error pulse,
the MDM shall send to the Drum Controller the first of the four byte pulses used to transfer the test
mode status word to the Drum Controller.
The Test Mode 1 status word format is as shown in
Figure 159.
(7) Whenever an error is detected the MDM shall have the
capability of detecting a sector end pulse (Logic 1) on the Sector End line. Upon detection of a sector
end pulse, the MDM shall continue on with the testing sequence of Test Mode 1 on subsequent tracks.
In the absence of a sector end pulse, the MDM shall remain in a state to continue testing on sub-
sequent tracks and shall send continuous error pulses, byte clocks and error data as shown by Note 5
of Figure 158.
(8) The MDM shall have the manual capability to allow forcing
a given number of known Test Mode 1 error status words during one complete operation of Test Mode 1.
MDM Test Mode 2 Sequence - The MDM Test Mode 2 timing
3.5.4.4.4.3.3.4.10.2
sequence is shown in the MDM Test Mode 2 timing diag r a m (Figure 160) and is described as follows:
(1) The Test Mode 2 signal becomes a Logic 1 and shall re-
main in the Logic 1 state for the entire duration of Test Mode 2 tests.
(2) After the Test Mode 2 signal the sector begin pulse is sent
to the MDM.
(3) After receipt of the sector begin pulse the MDM shall send
four byte clocks to the Drum Controller. Byte clocks 1 and 2 shall be used to transfer the input
stimulus data from the Drum Controller to the MDM and byte clocks 3 and 4 shall be used to transfer
the output response data from the MDM to the Drum Controller. The MDM Test Mode 2 status word
format is as shown in Figure 161.
(4) The parity error 3/4 pulses shall always occur as shown
on the timing diagram during a Test Mode 2 test. The parity error 3/4 pulses are forced parity errors
which indicate that the parity detect logic circuits are functioning properly.
(5) The parity error 1/2 pulses shall occur as shown on the
timing diagram if parity errors are detected during the processing of the input stimulus data during
Test Mode 2. The first parity error 1/2 pulse shall occur if a parity error is detected in the
serialized data; the second parity error 1/2 pulse shall occur if a parity error is detected in the
deserialized data.
(6) The preamble detect pulse shall always occur during Test
Mode 2 as shown in the timing diagram whenever the preamble detect circuitry is functioning properly.
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