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Parity Status Interrupt Word Format |
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|  MIL-D-81347C(AS)
(10) Bit 9 (Power Fault) shall be a Logic 1 when a fault exists
in the power conditions of the Magnetic Drum Memory power supply,
(11) Bit 8 (Track select Error) shall become a Logic 1 when
either more than one track is selected, no track is selected or a non-existent track is selected.
(12) Bit 7 (Clock Error) shall be a Logic 1 when the selected
clock timing is out of tolerance.
(13) Bit 6 (Pressure Error) shall be a Logic 1 when the pressure
in the Drum subassembly is below an acceptable level.
(14) Bit 5 (Overtemperature) shall be a Logic 1 when the tem-
perature of the Drum subassembly exceeds an acceptable level.
(15) Bit 4 (Speed Error) shall be a Logic 1 when the speed (or
speed related conditions) of the Magnetic Drum is out of tolerance.
(16) Bit 3 (Illegal Instruction) shall be a Logic 1 when the code
of an instruction is not one of those listed as a valid operation code or one of the test codes.
(17) Bit 2 (Write Lockout) shall become a logic,1 when any
portion of the memory addressed by a write instruction is a write protected section.
(18) Bit 1 (Address Error) shall be a Logic 1 when the begin
address of a read or write instruction is greater than or equal to the end address (Address Overflow)
or if a nonexistent track is addressed.
(19) Bit O (sequential/combinational Error) shall be a Logic 1
when the second word received in a two-word instruction is any word other than the correct one, master
clear, read/write terminate or when the second word of a two word instruction is received first.
Parity Status Interrupt Word Format
3.5.4.4.4.4.1.4
Figure 167 shows the format of the parity status interrupt word.
This word shall be sent to the computer following a Parity Status Request instruction. The contents
of the word reflect data of the first parity error detected during a read or write operation and shall be
as described below:
(1) Bit 29 (Parity Data Available) shall be a logic 1 if a parity
error is detected and data on that parity error is stored in these registers.
(2)
Bits 27 and 28 (Byte Designators) shall indicate in which
byte the first parity error was located. Only one of these two bits may be a logic 1 and only if the
first parity error detected occurred on data entering or leaving the drum.
(3) Bits 25 and 26 (Buffer Designators) shall indicate the
buffer from which the word containing the first detected parity error had been received. Only one of
these two bits may be logic 1 and only if the first parity error detected occurred on data retrieval
from one of the buffers.
(4) Bit 24 (Read/Write Mode) shall indicate the type of instruc-
tion being executed when the parity error was detected.
(5) Bits 19 through 23 are not used and shall be logic 0's.
(6) Bits 10 through 18 shall contain the address of the track
being used when the first parity error is detected. The contents of these nine bits have no meaning
when the first error detected is a buffer error.
(7)
Bits O through 9 shall contain the word address of the first
detected register parity error.
The contents of these 10 bits have no meaning when the first error
detected is a buffer error.
278
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