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Error Count Interrupt Word Format |
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|  MIL-D-81347C (AS)
Error Count Interrupt Word Format
3.5.4.4.4.4.1.5
Figure 168 shows the format of the Error Count Interrupt Word.
This word shall be sent to the computer following the execution of the Error Count Request instruction.
The contents of the word shall be as described below:
(1) Bit 29 (Error Count Data Available) shall be a logicl
when at least one parity error or an overrun/underrun condition has been detected and that error count
data is stored 'in these registers.
(2) Bits 20 through 28 (Overrun/Underrun count) shall be a
binary count of the number of times an overrun or underrun condition was detected. Bit 20 shall be
the least significant bit of the count. Acount of all 1's shall indicate that 511 or more such events
were detected.
(3) Bits 10 through 19 (Buffer Error Count) shall be a binary
count of the number of buffer parity errors detected. Bit 10 shall be the least significant bit of the
count. The count shall reincremented by one each time a buffer error (on a whole wordbasis)is
detected. Acount of all 1's shall indicate that 1023 or more buffer parity errors were detected.
(4) Bits 0 through 9 (Register Error Count) shall be a binary
count of the number of register parity errors detected. Bit 0 shall be the least significant bit of the
count. The count shall reincremented by one each time a register error (on a byte basis) is detected.
A count of all 1's shall indicate that 1023 or more register parity errors were detected.
Read/Write Data Word Formats
3.5.4.4.4.4.1.6
Figure 169 shows the relationship between the 30-bit data word
received from or sent to the computer and the 32-bit data word received from or sent to the magnetic
drum memory.
The 30-bit computer
word shall be divided into two 15-bit parts.
A parity bit P shall be added to computer bits 0 through 14
to form bits 0 through 15 (Byte 1) of the
drum word. A parity bit P1 shall be added to computer bits
15 through 29 to form bits 16 through 31
(Byte 2) of the drum word. Odd parity shall be used in the
generation of each of the parity bits.
Data transmission to and from the computer shall take place in
Data transmission to and from the selected drum track shall take
a 30-bit parallel transfer mode.
place in a serial mode.
Data Addressing
3.5.4.4.4.4.2
A total of 19 bits of address shall be used to specify the location
of a data word. Bits O through 9 of a read or write instruction shall be used to specify a particular
word out of 1024 on a track (bit O shall be the least significant bit). Bits 10 through 18 of a read or
write instruction shall be used to specify a particular track on the drum. Bit 10 shall be the least
significant bit of the track address. The lowest 384 of the possible 512 binary states of these nine bits
shall be used for track addressing.
A block of data to be written on or read from the drum shall be
specified by two addresses, namely a begin address (word and track) and an end address (word and
track). The begin address of an instruction shall specify the location at which a preamble word is to
be or has been written. Therefore, if it is desired to write or read a block of data with N data words
in the block, then the begin and end addresses of the instruction shall specify N + 1 address locations.
Data to be read from the drum shall be addressed in the same
manner used to specify addresses when it was written. When executing a read instruction, if a pre-
amble word is not detected at the begin address, the instruction shall be terminated and a Sync Detect
Error indicated to the computer.
279
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