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|  MIL-D-81347C(AS)
3.5.4.4.4.4.3
Data Buffers and Data Sectors
The Drum Controller shall include two 32-word (32 bits per
word)
data buffer in order to provide simultaneous data transfers. During a write instruction the
drum.
Conversely during a read of the buffers while the other buffer is being unloaded into the
drum.
Conversely during a read instruction the computer is unloading one of the-buffers while the
drum
is loading the other buffer.
Normally data will be transferred into and out of the buffers
in 32 word groups called data sectors. The loading of a buffer shall not be started until it is empty
and the unloading of a buffer shall not be started until it is full. However, the design of the Drum Con-
troller shall provide the capability for correctly writing and reading data sectors of any length as the
need arises. The situations where a variable length sector capability is required are those in which
the number of data words to be written or read is not an integral multiple of 32, i.e. , a data block
of 65 words would be written using two 32-word sectors and one 1-word sector.
Under normal circumstances, data transfer between the com-
puter and Drum Controller can take place at a substantially higher word rate than that between the
Drum and Drum Controller. Therefore, normally the computer will load/unload a buffer at a "Burst
Rate" and then wait until the Drum has unloaded/loaded the alternate buffer. If, for some reason such
as other program executions, the computer is unable to keep pace with the requirements of the Drum
for data, the Drum Controller shall sense the condition and cause data transfers to/from the drum to
cease until the Computer has had time to load/unload the buffer. This condition is called an Underrun
during a write instruction and an Overrun during a read instruction.
The Drum Controller shall count the number of such occur-
rences during the execution of a read or write instruction and retain the count in the Error Count
Status word.
Idle State and Interrupt Functions
3.5.4.4.4.4.4
While the Drum Controller is not actively executing an instruc-
tion it shall be in an idle state where internal controls are reset. Prior to the completion of all opera-
tional instructions, an Interrupt shall be sent to the Computer with the Instruction Status word or the
requested Status word in the cases of the Status Request instructions. All instructions, except Master
Clear and Read/Write Terminate shall start from the idle state and all instructions shall return the
Drum Controller to the idle state following their completion.
During the execution of a read or write instruction, if a parity
error is detected, an Interrupt with Instruction Status Word format shall be sent immediately to the
computer (interleaved with the IDR's in the case of a read instruction). However, this shall not term-
inate the instruction and the instruction shall be completed unless terminated by a subsequent com-
puter instruction.
Write Function Sequence
3.5.4 .4.4.4.5
The following is the sequence of steps which shall occur during
the execution of a write instruction:
( 1 ) The computer acknowledges the EFR and sends the first
word of the write instruction.
(2) The Drum Controller shall place a logic 0 on the EFR line
and shall check the instruction code. If the code is that of the second word of the write instruction, a
Sequential Error Interrupt shall be sent to the computer. When the instruction code is determined to
be that of the first word of the write instruction, the EFR line shall be placed at logic 1.
(3) The computer acknowledges the EFR and sends the second
word of the write instruction.
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