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| MIL-D-81347C(AS)
(4) The Drum Controller shall place a logic 0 on the EFR line
and shall check the instruction code. If the code is that of any instruction other than the second word
of the write instruction, master clear, or read/write terminate, a combinational Error Interrupt
shall be sent to the Computer. When it is determined that the second word of the write instruction has
been received, the addresses shall be checked for Address Error and Write Lockout Status. Detection
of any of these error conditions shall cause an Interrupt to be sent to the Computer. If no error con-
ditions are detected, the first data word shall be requested from the Computer.
(5) The Drum Controller shall place a logic 1 on the ODR line.
(6) The computer acknowledges the ODR and sends a 30-bit
data word.
(7) The Drum Controller shall place a logic 0 on the ODR line,
add the parity bits to the data word and place the 32-bit word in Buffer A.
(8) Steps (5), (6) and (7) shall be repeated until the buffer is
filled.
(9) At this time two things shall occur. The Drum Controller
shall start searching on the drum for the address where the data is to be written and the computer
starts to load Buffer B with the sequence indicated by steps (5), (6) and (7).
(10) When the begin address is located (within one revolution) on
the drum, the data in Buffer A shall be placed, one word at a time, into a parallel-to-serial register
and shifted serially into the drum. A parallel parity check shall be made on each data word as it is
placed into the register. A serial parity check shall be made on each byte of each data word as it is
shifted into the drum. The data flow to the drum shall continue until Buffer A is empty.
(11) At this time the contents of Buffer B shall be written on the
drum at their proper addresses in the same manner as described in step (10) and the computer loads
Buffer A as in steps (5), (6) and (7).
(12) This alternate loading and unloading of the buffers shall
continue until the Drum Controller has determined that the last addressed data word has been received
from the computer. The Drum Controller shall, when it senses that the last addressed data word has
been received, cease to send ODR signals to the computer and generate a full buffer condition if the
total number of data words addressed was not an integral multiple of 32.
(13) The Drum Controller shall cause write operations to cease
when it senses that the last addressed data word of the final buffer has been written.
(14) If, during the process of recording data on the drum, a
parity error is detected, the Drum Controller shall send an Instruction Status word with an Interrupt
to the computer indicating Parity Error Status as coon as the error is detected. The write operation
shall continue until it either has been completed or has been terminated by the computer.
(15) If, during the process of recording data, the computer is
unable to completely load one of the buffers by the time that the buffer contents must be written on the
drum, the Drum Controller shall cause the recording process to cease for whatever number of drum
revolutions (normally one) are needed for the computer to fill the buffer. This condition is called
Underrun (Computer under runs the drum) and each such occurrence shall be counted and the count
stored in the Error Count Status word.
(16) If no errors are detected during the instruction an
Instruction Status Word Interrupt shall be sent to the computer indicating Normal Completion Status.
(17) when the computer acknowledges the Interrupt the Drum
Controller shall reset the interrupt line and place a logic 1 on the EFR to the computer.
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