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|  MIL-D-81347C(AS)
3.5.4.4.4.4.6
Read Function Sequence
The following is the sequence of steps which shall occur during
the execution of a read instruction:
(1) The computer acknowledges the EFR and sends the first
word of a read instruction.
(2) The Drum Controller shall place a logic 0 on the EFR line
and shall check the instruction code. If the code is that of the second word of a read instruction, a
Sequential Error Interrupt shall be sent to the computer. When the instruction code is determined to
be that of the first word of a read instruction, a logic 1 shall be placed on the EFR line.
(3)
The computer acknowledges the EFR and send the second
word of the read instruction.
(4) The Drum Controller shall place a logic 0 on the EFR line
and shall check the instruction code. If the code is that of any instruction other than the second word
of a read instruction, master clear or read/write terminate, a Combinational Error Interrupt shall be
sent to the computer. When it has been determined that the second word of a read instruction has
been received, the addresses shall be checked for Address Error. If this condition is detected, an
Address Error Interrupt shall be sent to the computer. If no error condition is detected, the Drum
Controller shall start to search the drum for the begin address where a preamble word had been
written.
(5) If a preamble word is not detected (within one revolution)
at the begin address, a Sync Detect Error Status shall be sent with the Instruction Status Interrupt
word to the computer. If the preamble word is detected, the reading of data shall proceed.
(6) The data words shall be read from the drum in a serial
wanner and clocked into a serial-to-parallel register. As the words are placed into the register, each
byte of each word shall undergo a serial parity check.
As each 32 bit word is read, it shall be transferred into
(7)
Buffer A.
Steps (6) and (7) shall be repeated until Buffer A has been
(8)
filled with 32 data words.
(9)
The Drum Controller shall now switch to load Buffer B
and shall proceed as described in steps (6), (7) and (8).
(10) The Drum Controller shall place a word from Buffer A
on the computer Data Input lines and a logic 1 on the IDR line to the computer . As the data word is read
from the buffer, a parallel parity check shall be made on the 32-bit word. The two parity bits shall
be removed and the remaining 30-bit word shall be sent to the computer,
(11)
The computer accepts the data word and acknowledges the
IDR signal.
(12) The Drum Controller shall place a logic 0 on the IDR line
and shall increment to the next word in Buffer A.
(13) Steps (10), (11) and (12) shall be repeated until all 32
words in Buffer A have been sent to the computer.
(14) As soon as the drum has filled Buffer B, two things shall
occur. The computer unloads Buffer B as described in steps (10), (11) and (12) and the drum shall
load Buffer A as described in steps (6), (7) and (8).
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