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|  MIL-D-81347C(AS)
(15) This alternate loading and unloading of the buffers shall
continue until the Drum Controller has determined that the last addressed data word has been received
from the drum. The Drum Controller shall, when it senses that the last addressed data word has
been received from the drum, cease to react data from the drum and generate a full buffer condition if
the total number of data words addressed was not an integral multiple of 32.
(16) The Drum Controller shall send data to the Computer as
described in steps (10), (11) and (12) until the last addressed word of the final buffer has been trans-
mitted to the computer.
(17) If, during the process of reading data from the drum, a
parity error is detected, the Drum Controller shall send an Instruction Status word with Interrupt to
the computer indicating parity error status as soon as the error is detected. This Interrupt shall be
interleaved with the IDR signals to the computer with no loss of data. The read operation shall con-
tinue until it either has been completed or has been terminated by the computer.
(18) If, during the process of reading data, the computer is
unable to empty a buffer by the time it is required by the drum for the next data sector, the Drum
Controller shall cause the reading process to cease for whatever number of drum revolutions (nor-
mally one) are needed for the computer to empty the buffer. This condition is called Overrun (Drum
overruns the computer) and each such occurrence shall be counted and the count stored in the Error
Count Status word.
(19) If no errors are detected during the instruction, an Instruc-
tion Status Interrupt shall be sent to the computer indicating Normal Completion Status.
(20) When the computer acknowledges the Interrupt, the Drum
Controller shall reset the Interrupt line, and place a logic 1 on the EFR line to the computer.
Master Clear Function
3.5.4.4.4.4.7
The Master Clear Instruction shall be executed either in
response to the EFR from the Drum Controller or by use of an E F with Force from the computer,
This instruction shall cause any instruction in process to be
terminated and shall cause all status error data to be cleared. The contents of the Memory Protect
Register shall not be altered by this instruction.
An Interrupt with the Instruction Status word shall be sent to the
computer. After the computer acknowledges the Interrupt, the Drum Controller shall reset the
Interrupt line and place a logic 1 on the EFR line to the computer.
Read/Write Terminate Function
3.5.4.4.4.4.8
The Read/Write Terminate Instruction shall be executed either
in response to the EFR from the Drum Controller or by use of EF with Force from the computer.
This instruction shall cause a read or write instruction to be
terminated but all status and error data shall remain unchanged.
An Interrupt with the Instruction Status word shall be sent to the
computer. After the computer acknowledges the Interrupt, the Drum Controller shall reset the
Interrupt line and place a logic 1 on the EFR line to the computer.
3.5.4.4.4.4.9
Status Function
The Instruction Status Interrupt word shall be sent to the com-
puter following all operational instructions except for the two status request instructions. The status
request instructions shall be executed as follows:
(1) The computer acknowledges the EFR and sends a status
request instruction code (either Parity or Error Count).
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