Programming procedure for circuit G.

Page Title: Programming procedure for circuit G.
Back | Up | Next

Web
www.tpub.com

Information Categories

....

MIL-M-38510/207E

4.10 Programming procedure for circuit G. The programming characteristics on table IVG and the following

procedures shall be used for programming.

a. Connect the device in the electrical configuration of programming. The waveforms on figure 5D and the

programming characteristics of table IVG shall apply to these procedures.

b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the

device by applying a high level to one or more active low chip enable inputs. NOTE: Address and enable

inputs must be driven with TTL logic levels during programming and verification.

c. Increase VCC from nominal to VCCP (10.5 0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/μs). Since

VCC is the source of the current required to program the fuse, as well as the ICC for the device at the

programming voltage, it must be capable of supplying 750 mA at 11.0 volts.

d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 0.5 V). Limit

the slew rate to IRR (1.0 to 10.0 V/μs). This voltage change may occur simultaneously with the VCC

increase to VCCP, but must precede it. It is critical that only one output at a time be programmed since the

internal circuits can only supply programming current to one bit at a time. Outputs not being programmed

must be left open or connected to a high impedance source of 20 kΩ minimum (remember that the outputs

of the device are disabled at this time).

e. Enable the device by taking the chip enable(s) to a low level. This is done with a pulse PWE for 10 μs.

The 10 μs duration refers to the time that the circuit (device) is enabled. Normal input levels are used and

rise and fall times are not critical.

f. Verify that the bit has been programmed by first removing the programming voltage from the output and

then reducing VCC to 5.0 V (0.25 V). The device must be enabled to sense the state of the outputs.

During verification, the loading of the output must be within specified IOL and IOH limits.

g. If the device is not to be tested for VOH over the entire operating range subsequent to programming, the

verification of step f is to be performed at a VCC level of 4.0 volt ( 0.2 V ). VOH, during the 4 volt

verification, must be at least 2.0 volts. The 4 volt VCC verification assures minimum VOH levels over the

entire operating range.

h. Repeat steps 4.10b through 4.10f for each bit to be programmed to a high level. If the procedure is

performed on an automatic programmer, the duty cycle of VCC at the programming voltage must be limited

to a maximum of 25%. This is necessary to minimize device junction temperatures. After all selected bits

are programmed, the entire contents of the memory should be verified.

i. For class S and B devices, if any bit does not verify as programmed it shall be considered a programming

reject.

Integrated Publishing, Inc. - A (SDVOSB) Service Disabled Veteran Owned Small Business