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Page Title:
Figure 4. Read cycle, write cycle, read/modify/write cycle waveforms and truth tables. |
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|  MIL-M-38510/245B
TRUTH TABLE
Inputs
Output
Time
reference
Function
A
Q
CE
W
H
X
-1
X
Z
Memory disable
H
0
V
Z
Cycle begins, addresses are latched
1
L
H
X
X
Output enabled
2
L
H
X
V
Output valid
3
H
X
V
Read accomplished
4
H
X
X
Z
Prepare for next cycle (same as -1)
5
H
V
Z
Cycle ends, next cycle begins (same as 0)
The address information is latched in on the chip registers on the falling edge of CE (T = 0). Minimum address set
up and hold time requirements must be met. After the required hold time, the addresses may change state without
affecting device operation. During time (T = 1) the output becomes enabled but data is not valid until during time (T
= 2). W must remain high until after time (T = 2). After the output data has been read, CE may return high (T =
3). This will disable the output buffer and ready the SRAM for the next memory cycle (T = 4).
NOTE: See figure 5 for test conditions.
FIGURE 4. Read cycle, write cycle, read/modify/write cycle waveforms and truth tables.
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