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A. Apply input pulse:
2.5 V minimum/5.5 V maximum
0V
B. VIN = 2.4 V.
C. VIN = 0.4 V.
D. Test numbers 57 through 79 shall be run in sequence.
E. Output voltages shall be either: (1) H ≥2.5 V minimum and L ≤0.4 V maximum when using a high speed checker double comparator; (2) H ≥1.5 V and L <1.5 V when using a high
speed checker single comparator.
F. fMAX minimum limit specified is the frequency of the clock input pulse. The output frequency shall be one-half of the input clock frequency. The input frequency on the serial shall be
one-half of the clock input frequency and the serial shall be shifted such that the serial ↑ and ↓ are coincident with the clock ↑ . Rise and fall times ≤ 6 ns. Input peak voltage 3 to 5
volts.
G. 3.0 V minimum/5.0 V maximum.
1/ IIL limits (mA) min/max values for circuits shown:
Parameter
Terminal
A
B
C
D
E
IIL1
Serial
-.075/-.250
-.16/-.40
-.16/-.40
-.105/-.345
-.12/-.36
-.12/-.36
-.16/-.40
-.16/-.40
-.105/-.345
-.12/-.36
AIN, BIN,
CIN, DIN
Mode
-.16/-.40
-.15/-.38
-.03/-.3
-.12/-.36
-.12/-.36
CONT
-.16/-.40
-.16/-.40
-.03/-.3
-.12/-.36
-.12/-.36
CLK
-.16/-.40
-.20/-.44
-.03/-.3
-.12/-.36
-.12/-.36
2/ IOS limits (mA) min/max values for circuit A: -30/-130.
for circuits B, C, D, E: -15/-100.
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