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|  MIL-M-63320A(AR)
4 . 5 . 9 Output low. W h e n the outputs at pins (3, 4, 5, 6, 7, 9,
1 2 , 14) are sinking current and held at 1.0 volt, measure the
c u r r e n t into each pin. A n y device failing to meet the min current
r e q u i r e m e n t of 3.5.2.6/3.5.2,7/3. 5.2.8 shall be classed defective.
( N o n - d e s t r u c t i v e test).
4 . 5 , 1 0 Output high. W h e n the outputs at pins (3, 4, 5, 6, 7,
9, 1 2 and 14) are sourcing currents and held at (V D D - 1.0) volts,
m e a s u r e the current out of each pin. Any device failing to meet the
m i n current requirement of 3.5.2.9/3.5.2.10 shall be classed
defective. (Non-destructive
test).
4 . 5 . 1 1 Switching points . ( P i n 2). Measure the switching
points at pin 2 in accordance with the test sequence of Table V and
with the device connected as shown in Figure 3. A n y device failing
to meet the switching requirement between the max and min voltage
l e v e l s of 3.5.2.11 shall be classed defective. ( N o n - d e s t r u c t i v e
test).
4 . 5 . 1 2 Switching p o i n t . (Pin 13). With pin 16 connected to
7 . 5 volts and pin 8 connected to V SS (ground), set pin 13 at 2.5
v o l t s and confirm that the output voltage @ Pin 12 is less than 1.5
v o l t s . S e t pin 13 to 5.0 volts and confim that the output voltage
a t pin 12 is greater than 6 volts. Any device failing to meet the
m i n and max voltage requirements of 3.5.2.12 shall be classed
defective,
( N o n - destructive test).
4 . 5 . 1 3 Noise immunity. N o i s e immunity at input pins (1, 10,
11, 1 5 ) shall be confirmed during the functional tests (see 4.5.14).
A n y device failing to meet the min noise voltage requirements of
3 . 5 . 2 . 1 3 for a VD D of 5.0/7.5 volts shall be classed defective.
( N o n - d e s t r u c t i v e test).
4 . 5 . 1 4 F u n c t i o n a l t e s t s . T h e functional tests consist of ten
s e q u e n t i a l tests defined in Figure 5 thru 14. T e s t s defined by
F i g u r e 1 and 2 shall be run at V D D = 5.0 volts and 7.5 volts; all
o t h e r tests are to be run at 5.0 volts. A t VD D 5.0, input low
a n d high logic levels shall be 1.0 volt and 4.0 volts respectively;
o u t p u t low logic level shall be less than 1.0 volts and output high
l o g i c level greater than 4.0 volts. A t VD D
7.5 volts, input low
a n d high logic levels shall be 1.5 volts and 5.0 volts respectively;
o u t p u t low and high logic levels shall be less than 1.5 volts and
g r e a t e r than 5.0 volts respectively. A n y device failing to meet the
r e q u i r e m e n t s of 3.5.3 shall be classed defective. ( N o n - d e s t r u c t i v e
test).
4 . 5 . 1 5 O s c i l l a t o r f u n c t i o n t e s t . The device shall be connected
a s shown in Figure 1 and tested for the requirements as specified in
3 . 5 . 4 . A n y device failing to meet the requirement of 3.5.4 shall be
c l a s s e d d e f e c t i v e . ( N o n - d e s t r u c t i v e test).
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