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|  MIL-T-63520(AR)
3.8.5.3 Interlocked trigger. With the input power specified in Table I
and the normal logic signals specified in Table V, the voltage at Pin J3-c
shall be 28.0 -+0.5 Vdc. When a 28 Vdc signal is applied to Pin J1-N, the
voltage at Pin J3-c shall be 5.0 + 1.0 Vdc. When any one or more of the logic
signals specified in Table VI areabnormal, the voltage at Pin J3-c shall be
28.0 + 0.5 Vdc independent of the voltage input at Pin J1-N.
3.8.5.4 Trigger application. With input power as specified in Table I,
normal logic inputs as specified in Table V and a 28 Vdc trigger signal is
applied, the following output characteristics shall occur:
a. The voltage at Pin J2-D shall be 1.O + 1.O Vdc within 2 ms after
applying 28 Vdc at Pin J1-N.
b. The voltage at Pin J1-K shall be 1.0 + 1.0 Vdc within 35 ms after
applying 28 Vdc at Pin J1-N.
c. With no dynamic load (see 3.8.7) on Pin J2-A, the voltage at Pin
J2-A shall be 350 + 50 Vdc within 40 ms after applying 28 Vdc at Pin J1-N.
d. The voltage at Pin J2-H shall be 1.0 + 1.O.Vdc within 40 ms after1
applying 28 Vdc at Pin J1-N.
e. The voltage on J3-c shall be 5.0 + 1.0 Vdc within 1.5 ms after
applying 28 Vdc at Pin J1-N.
3.8.5.5 Trigger signal revoval. The following output characteristics
shall occur when the input at Pin J1-N changes from 28 Vdc to 0 Vdc with input
power specified in Table I and normal Logic Signals specified in Table V.
(Note: Pin J1-N must be maintained at 28 Vdc for a minimum of 100 ms prior to
a transition to O Vdc).
a. The voltage at Pin J2-D shall be 28.0 + 5 Vdc within 11 ms after
removing the 28 Vdc at Pin J1-N.
b. The voltage at Pin J1-K shall remain at 1.0 + 1.0 Vdc for 750+250
ms after removing the 28 Vdc at Pin J1-N. After the above delay, the voltage
at Pin J1-K shall be 28 + 1 Vdc.
c. The voltage at Pin J2-A shall remain at 350 +50 Vdc for 1.5 +0.5
seconds after removing the 28 Vdc at Pin J1-N. After theabove delay, the
voltage at Pin J-2A shall be O Vdc.
d. The voltage at Pin J2-H shall be 24 + 2 Vdc within 2 ms after the
voltage at Pin J2-A falls below 100 Vdc.
e. The voltage at Pin J3-c shall be 28.0 + 5 Vdc within 1.5 ms after
removinq the 28 Vdc at Pin J1-N.
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