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|  MIL-W-85057(AS)
3.4.1.4.4.2 Direct Input/Output. The transfer of I/0 data between the
CIU and the DC accumulator register shall be performednder software control.
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3.4.1.4.5 Data Transfer Rates. The data transfer rates for the two
processing modes of 3.4.1.3.4 shall be at least as follows:
Mode
Data Transfer Rate
Buffered I/0
125K words/second
Direct I/0
200K words/second
The data transfer rate for the buffered I/0 mode shall be obtained under the
condition that no concurrent DC instruction execution is being performed.
3.4.1.5 Throughput. The WDC shall be capable of executing the instruction
set defined in 3.4.1.2 at the speed specified in 3.4.1.3.
3.4.1.5.1 Throughput with Buffered Input/Output. The WDc shall execute
requests for external buffered I/0 with an overhead not greater than 10 us
for the first word in a block and not more than 5 us for each word thereafter.
3.4.1.6 Programability. The WDC shall be capable of being programmed
by making use of the instruction set defined in 3.4.1.2.
3.5 Detail Requirements.
3.5.1 Digital Computer. The Digital Computer(DC), Type CP-1276/ASB-19(V),
as a component of the WDC, shall provide the following:
3.5.1.1 Machine Organization. Machine organization within the DC shall
contain, as a minimum, the following: a binary, fixed point, two's complement,
fractional number system; full parallel (16 bits) operation; 6 registers
(A, Q, B, IC, O/D, and INTF); and direct, indirect, indexed (base relative),
instruction counter (IC) relative, and Immediate addressing modes. The A, Q,
and B registers shall be capable of being loaded from or to memory, and the
IC register shall contain the absolute address of the next memory location
to be fetched as as instruction at the time that the current instruction iS
beginning execution. The contents of the XC register may be changed by branch
Instructions and interrupts.
3.5.1.2 Direct Memory Access (DMA) Capability. The DMA data transfer
rate shall be at least 500,000 words per second. The DC shall be capable of
a DMA data transfer rate of 250,000 words per second and concurrently executing
150,000 instructions per second, using an Instruction mix of 76% ADD (1/2 Indirect),
18% Branch (1/2 Taken), 5% MDY (1/2 Indirect), and l% Divide (1/2 Indirect).
3.5.1.3 Memory.
3.5.1.3.1 Addressability. All words of the main memory shall be
contiguously addressed from 0000 to 7FFF hexadecimal.
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