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|  MIL-W-85057 (AS)
3.5.1.3.2 Memory Speed. The memory read/restore cycle time shall be no
more than 1.00 us maximum with a 500-nanosecond (ns) maximum direct access
time. The memory shall operate in three modes as follows:
Mode
Function
Store:
Storage of correct data in an
addressed location.
Read/restore:
Obtain data from an addressed
location In storage without
altering the contents of the
storage location.
Read/compute/write:
Read data from an addressed
location, cause memory to pause
while the data is being used by
the processor to generate new
data, and then store the new
data in the previously addressed
location.
3.5.1.4 Central Processor (CP). The internal logic of the CP shall
utilize data bits that are internally generated or transferred, or both,
in a parallel mode, and all 1/0 comunications shall be executed in a
parallel mode. The internal logic shall be capable of generating and
handling both positive and negative numbers with l qual ease and execution
time. Programmer access to the internal logic for all required operations
.
shall be by means of the instruction set defined in 3.4.1.2.
3.5.1.4.1 Loading/Storing of Registers. Loading/storing from or into
memory locations shall be accomplished from any one of three registers
(A, B, or Q). These registers are defined herein.
3.5.1.4.2 Arithmetic Operations. The DC shall be capable of executing
the following two's complement arithmetic operations:
Addition: Adding of two single word operands to
(1)
.
generate a single word sum, and adding two double
length operands to generate a double length sum.
Subtraction: Subtracting two single word operands
(2)
to generate a single word difference, and subtracting
two double length operands to generate a double length
difference.
.
Multiplication: Multiplying a single word multiplicand
(3)
(positive or negative) by a single word multiplier (positive
or negative) to yield a double word true product.
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