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|  MIL-W-85057(AS)
3.5.1.4.5 Branch (Jump) Operations. The DC shall provide for, as a
minimum, branch operations (jump shell herein be referred to as branch) in
program execution address with the following operation:
Unconditional branch: Shall have an instruction which
(1)
loads the instruction counter register with a designated
memory address and be possible to specify the address
of any memory location.
(2)
Conditional branch: Shall test the accumulator register
either for contents negative (alternately equal to zero)
and modify the instruction counter according to the
results of the test.
Subroutine branch: Shall transfer control to a subroutine
(3)
at any point while saving the l ddress of the instruction
following the subroutine branch Instruction and shall
nest subroutine cane to at least four levels.
Increment and branch: Shall increment a register or
(4)
memory location and cause a branch to take place when
the contents reach zero.
3.5.1.4.6 Input/Output Operations. The DC shall have an instruction
that causes a single word operand to be placed on or accepted on the DC I/0
bus. The source or destination of the operand shall be the accumulator
register.
3.5.1.5 Registers. As a minimum, the DC shall have six registers. Each
register shall contain at least 16 bits. When more than the minimum number
of registers are provided, they may share the functions below.
3.5.1.5.1 Accumulator Register (A-REG). The A-REG shall be a register
that can be loaded from, or into memory, and:
(1) Contains the result of single precision sold/subtract
operation.
(2) Contains the result of logical and shift operations.
(3) Contains one parameter for add/subtract and logical
operations.
{4) Used in multiply/divide operations.
3.5.1.5.2 Base Register (B-REG). The B-REG shall coatain the base
address and be loaded from storage, placed in storage, and added to operands
from storage. Contents of the B-REG may be moved to or from the A-REG.
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